Noise shaped to high-frequency area. Hence, relevant circuits in Figure 3aNoise shaped to high-frequency area.

Noise shaped to high-frequency area. Hence, relevant circuits in Figure 3a
Noise shaped to high-frequency area. Therefore, relevant circuits in Figure 3a are modified such that the output within the AS-0141 manufacturer digital domain, whose high-frequency quantization noise is suppressed by a digital low-pass filter (LPF), is often added for the quantizer output as depicted in the dotted box of Figure 3b, that is known as digital feedback residue quantization (DFRQ) strategy.Electronics 2021, ten,four ofFigure 3. Proposed swing reduction approaches: (a) digital input feedforwarding and (b) digital feedback residue quantization.The resulting outputs of the DSM in Figure 3a,b might be written as: V (z) = U (z) 1 1 E (z) E (z) 1 H (z) Q1 1 H (z) Q2 (1)V (z) =1 H (z) ( z ) E (z) 1 H (z) – G (z) 1 H (z) – G (z) Q(two)In Equation (two), the very first and second terms on the right-hand side represent the STF and NTF, respectively. In this equation, note that, if G (z) = 1, then STF 1, which implies = that the proposed DSM with DFRQ can supply exactly the same STF as that in the conventional input feedforwarding inside the passband range of the digital LPF. Thus, by employing the digital feedback of your low pass-filtered DSM output as inside the proposed DSM, the quantizer may be produced to procedure only the residual quantization noise. As described in Section 1, the continuous-time ADC utilizing Etiocholanolone supplier VCO-based quantizer is often a good candidate as a high-speed low-power ADC however the VCO nonlinearity can be a limiting factor. At this point, it’s worth noting that the decreased voltage swing from the quantizer input from the proposed DFRQ lends itself to become effectively suited with VCO-based quantizer. Figure 4 shows the block diagram in the resulting VCO-based CT ADC adopting the proposed DFRQ. The DSM is composed of a CT loop filter with a second-order RC integrator, a five-bit feedback DAC, a VCO-based quantizer, a digital finite-impulse response (FIR) filter, a digital adder, in addition to a truncator. By the proposed configuration, the third-order noise shaping is implemented by the second-order loop filter as well as the first-order intrinsic noise-shaping of your VCO-based quantizer. The structure with the VCO-based quantizer is shown in Figure 5, which consists of a starved inverter-based ring oscillator and counters. It can supply a quantized digital version of the analog input voltage by counting the number of oscillation edges in each and every clock cycle. The digital low-pass filtering to suppress high frequency quantization noise is implemented by a digital adder right after the VCO-based quantizer and also the digital FIR filter in the output on the DSM. The structure of your FIR filter is shown in Figure 6a, that is implemented applying 4 taps. The timing constraint on the proposed DFRQ to make sure loop stability from the digital feedback composed in the -truncator and LPF calls for that the DFRQ really should operate in one particular clock cycle. To ensure the overall loop stability of CT DSMs, an excess loop delay (ELD) compensation scheme is often applied [168].Electronics 2021, 10,five ofFigure four. VCO-based CT ADC with DFRQ.Figure 5. VCO-based quantizer.Figure six. (a) Four-tap digital FIR filter, (b) first-order truncator.To sufficiently suppress the residual quantization noise within the DFRQ, the FIR filter having a bigger quantity of taps really should be utilized, resulting in an elevated quantity of output bits. This also increases the levels of the feedback DAC, growing the complexity from the DAC and tightening the timing requirement imposed around the DWA and DAC operation. Consequently, the quantizer along with the feedback DAC may possibly consume a large dynamic power.